As electronic equipment becomes smaller in size and thinner, there is a demand for increases in the packaging density of semiconductor packages. For this reason, conventional semiconductor packages have progressed from types such as DIPs, which are mounted by insertion of leads, to surface mounted types such as QFPs which enable high-density packaging. With a semiconductor package having leads such as QFPs, the space of connection between a printed circuit board and the leads of the semiconductor package cannot be effectively utilized. Therefore, in recent years, semiconductor packages of the area array terminal type such as BGAs and CSPs in which the semiconductor package does not have leads and which is directly bonded to a printed circuit board using solder ball electrodes under the package are becoming predominant.
Among semiconductor packages of the area array terminal type such as BGAs and CSPs, taking BGAs as an example, the classes which are prevailing and currently most widely used are PBGAs (Plastic BGAs) in which a semiconductor chip is connected to a plastic substrate by wire bonding using wires such as gold wires and TBGAs (Tape BGAs) in which a polyimide tape is used instead of wires. However, with PBGAs or TBGAs, connections such as wires or a tape are disposed so as to extend to the exterior of a silicon chip. As a result, solder ball electrodes formed on a substrate are gathered on the outer sides of a silicon chip, and solder ball electrodes can not be disposed on the surface of a silicon chip. In order to solve this drawback, FBGAs (Flip Chip BGAs) which can achieve reductions in size and increases in the density of semiconductor packaging have recently come to be used.
In contrast to PBGAs or TBGAs in which wiring is on the upper side of a silicon chip, in FBGAs, solder bumps are provided on electrodes on the underside of a silicon chip, and a semiconductor package is manufactured by performing contact bonding of the solder bumps with a preliminary solder provided on the top face of an insulating substrate. Since FBGAs have no wiring which is extended from the sides of a silicon chip as in a PBGA or TBGA, it is possible to manufacture a semiconductor package which is close to the size of a silicon chip.
In the past, a Sn—Pb based high-temperature solder such as Pb-5Sn has been used as a solder for flip chip bumps formed on the electrodes on the underside of a silicon chip. A Sn—Pb based solder has good elongation properties and excellent heat cycle properties. However, as the effects of lead on the human body become known, the use of lead is becoming a global environmental problem because lead easily dissolves in water. Accordingly, there is a demand for a lead-free solder material and a structure made thereof which can replace Sn—Pb solder, which has excellent properties and particularly resistance to thermal fatigue, which endures without damage to elements, parts, or the like at the time of soldering and at the time of a heat cycle test, and which has excellent solderability.
In order to cope with this problem, a Sn-3Ag-0.5Cu lead-free solder composition which is extensively used for mounting of printed circuit boards has been studied as a lead-free solder for flip chip bumps. Solder bumps used for flip chip bonding of semiconductor packages often have a silicon chip above them and an insulating substrate made of a ceramic such as alumina or a glass epoxy material such as FR-4 below them. Solder alloys have a different coefficient of thermal expansion from a ceramic or a glass-epoxy resin. If a Sn-3Ag-0.5Cu lead-free solder, which is relatively hard and has poor stress relaxation properties compared to a Sn—Pb based solder, is used in such places, peeling easily develops between the flip chip connection structure and the insulating substrate due to heat cycles, leading to problems with respect to reliability.
It has been reported that with a lead-free solder such as Sn-3Ag-0.5Cu solder, so-called Cu erosion occurs more readily than with a conventional Sn—Pb solder. Cu erosion is a phenomenon in which Cu electrodes such as Cu plating formed atop an insulating substrate dissolve in Sn at the time of reflow soldering, and it results in peeling easily taking place between the chip connection structure and the insulating substrate. Cu erosion takes place more easily as the melting temperature of solder increases. Technologies which have been disclosed for solving this problem include a semiconductor assembly which uses a low-temperature lead-free solder such as Sn—In, Sn—Bi, Sn—Zn, or Sn—Zn—Bi (JP 2007-141948 A, Patent Document 1) and a connection structure which uses a low-temperature lead-free solder composition in the form of a Sn—Ag—Cu—In—Bi solder composition (JP 2001-35978 A, Patent Document 2).
Patent Document 1: JP 2007-141948 A
Patent Document 2: JP 2001-35978 A